Package nl.kbna.dioscuri.module.cpu

Interface Summary

Instruction

Class Summary

CPU	An implementation of an Intel 8086 hardware CPU module.
Instruction_2ByteEscape	Intel opcode 0F Escape character for two-byte opcodes.
Instruction_AAA	Intel opcode 37 AAA- ASCII adjust after addition.
Instruction_AAD_Ib	Intel opcode D5 ASCII adjust AX before division.
Instruction_AAM_Ib	Intel opcode D4 ASCII adjust AX after multiply.
Instruction_ADC_ALIb	Intel opcode 14 Add (immediate byte + CF) to AL.
Instruction_ADC_AXIv	Intel opcode 15 Add (immediate word + CF) to AX.
Instruction_ADC_EbGb	Intel opcode 10 Add byte (+ CF) in register (source) to memory/register (destination).
Instruction_ADC_EvGv	Intel opcode 11 Add word in register (source) + CF to memory/register (destination).
Instruction_ADC_GbEb	Intel opcode 12 Add byte in memory/register (source) + CF to register (destination).
Instruction_ADC_GvEv	Intel opcode 13 Add word in memory/register (source) + CF to register (destination).
Instruction_ADD_ALIb	Intel opcode 04 Add immediate byte to AL.
Instruction_ADD_AXIv	Intel opcode 05 Add immediate word to AX.
Instruction_ADD_EbGb	Intel opcode 00 Add byte in register (source) to memory/register (destination).
Instruction_ADD_EvGv	Intel opcode 01 Add word in register (source) to memory/register (destination).
Instruction_ADD_GbEb	Intel opcode 02 Add byte in memory/register (source) to register (destination).
Instruction_ADD_GvEv	Intel opcode 03 Add word in memory/register (source) to register (destination).
Instruction_AND_ALIb	Intel opcode 24 Logical AND of immediate byte and AL.
Instruction_AND_AXIv	Intel opcode 25 Logical AND of immediate word and AX.
Instruction_AND_EbGb	Intel opcode 20 Logical byte-sized AND of memory/register (destination) and register (source).
Instruction_AND_EvGv	Intel opcode 21 Logical word-sized AND of memory/register (destination) and register (source).
Instruction_AND_GbEb	Intel opcode 22 Logical byte-sized AND of register (destination) and memory/register (source).
Instruction_AND_GvEv	Intel opcode 23 Logical word-sized AND of register (destination) and memory/register (source).
Instruction_ARPL_EwGw	Intel opcode 63 Adjust RPL Field of Segment Selector.
Instruction_BOUND_GvMa	Intel opcode 62 Check array index against bounds.
Instruction_CALL_Jv	Intel opcode E8 Call to procedure within the current code segment (intrasegment call) indicated by immediate signed word.
Instruction_CALLF_Ap	Intel opcode 9A Call to procedure in another code segment (intersegment call) indicated by immediate signed words.
Instruction_CBW	Intel opcode 98 Convert byte to word.
Instruction_CLC	Intel opcode F8 Clear carry flag.
Instruction_CLD	Intel opcode FC Clear direction flag.
Instruction_CLI	Intel opcode FA Clear interrupt flag.
Instruction_CMC	Intel opcode F5 Complement carry flag.
Instruction_CMP_ALIb	Intel opcode 3C Comparison of immediate byte (SUB) with AL.
Instruction_CMP_AXIv	Intel opcode 3D Comparison of immediate word (SUB) with AX.
Instruction_CMP_EbGb	Intel opcode 38 Byte-sized comparison (SUB) of memory/register ("destination") with register (source).
Instruction_CMP_EvGv	Intel opcode 39 Word-sized comparison (SUB) of memory/register ("destination") with register (source).
Instruction_CMP_GbEb	Intel opcode 3A Byte-sized comparison (SUB) of register ("destination") with memory/register (source).
Instruction_CMP_GvEv	Intel opcode 3B Word-sized comparison (SUB) of register ("destination") with memory/register (source).
Instruction_CMPS_XbYb	Intel opcode A6 Compare string byte at address DS:(E)SI with address ES:(E)DI.
Instruction_CMPS_XvYv	Intel opcode A7 Compare string word at address DS:(E)SI with address ES:(E)DI.
Instruction_CWD	Intel opcode 99 Convert Word to DoubleWord.
Instruction_DAA	Intel opcode 27 DAA - Decimal adjust AL after addition.
Instruction_DEC_AX	Intel opcode 48 Decrement general register AX.
Instruction_DEC_BP	Intel opcode 4D Decrement general register BP.
Instruction_DEC_BX	Intel opcode 4B Decrement general register BX.
Instruction_DEC_CX	Intel opcode 49 Decrement general register CX.
Instruction_DEC_DI	Intel opcode 4F Decrement general register DI.
Instruction_DEC_DX	Intel opcode 4A Decrement general register DX.
Instruction_DEC_SI	Intel opcode 4E Decrement general register SI.
Instruction_DEC_SP	Intel opcode 4C Decrement general register SP.
Instruction_ENTER_IwIb	Intel opcode C8 ENTER — Make Stack Frame for Procedure Parameters.
Instruction_ESC_FPU	Intel opcodes D8 - DF Escape to coprocessor instruction set (Floating Point Unit, FPU).
Instruction_GRP11_MOV_EbIb	Intel opcode C6 Group 11 opcode extension: MOV immediate byte (source) into memory/register (destination).
Instruction_GRP11_MOV_EvIv	Intel opcode C7 Group 11 opcode extension: MOV immediate word (source) into memory/register (destination).
Instruction_GRP6	Intel opcode 0F 00 Group 6 opcode extension: SLDT, STR, LLDT, LTR, VERR, VERW.
Instruction_GRP7	Intel opcode 0F 01 Group 7 opcode extension: SGDT, SIDT, LGDT, LIDT, SMSW, LMSW, INVLPG.
Instruction_HLT
Instruction_ImmGRP1_EbIb	Intel opcode 80 Immediate Group 1 opcode extension: ADD, OR, ADC, SBB, AND, SUB, XOR, CMP.
Instruction_ImmGRP1_EvIb	Intel opcode 83 Immediate Group 1 opcode extension: ADD, OR, ADC, SBB, AND, SUB, XOR, CMP.
Instruction_ImmGRP1_EvIv	Intel opcode 81 Immediate Group 1 opcode extension: ADD, OR, ADC, SBB, AND, SUB, XOR, CMP.
Instruction_IMUL_GvEvIb	Intel opcode 6B Signed multiply.
Instruction_IMUL_GvEvIv	Intel opcode 69 Signed multiply.
Instruction_IN_ALDX	Intel opcode EC Put byte from I/O port address specified by DX into AL.
Instruction_IN_ALIb	Intel opcode E4 Put byte from I/O port address indicated by immediate byte into AL.
Instruction_IN_eAXDX	Intel opcode ED Put word/doubleword from I/O port address specified by DX into eAX.
Instruction_INC_AX	Intel opcode 40 Increment general register AX.
Instruction_INC_BP	Intel opcode 45 Increment index register BP.
Instruction_INC_BX	Intel opcode 43 Increment general register BX.
Instruction_INC_CX	Intel opcode 41 Increment general register CX.
Instruction_INC_DI	Intel opcode 47 Increment index register DI.
Instruction_INC_DX	Intel opcode 42 Increment general register DX.
Instruction_INC_SI	Intel opcode 46 Increment index register SI.
Instruction_INC_SP	Intel opcode 44 Increment index register SP.
Instruction_INCDEC_GRP4	Intel opcode FE INC/DEC Group 4 opcode extension: INC, DEC.
Instruction_INCDEC_GRP5	Intel opcode FF INC/DEC Group 5 opcode extension: INC, DEC, CALLN, CALLF, JMPN, JMPF, PUSH.
Instruction_INSB_YbDX	Intel opcode 6C Copy word from I/O port to ES:DI; update DI register according to DF.
Instruction_INSW_YvDX	Intel opcode 6D Copy word from I/O port to ES:DI; update DI register according to DF.
Instruction_INT_Ib	Intel opcode CD Call to Interrupt Procedure.
Instruction_INT3	Intel opcode CC Call to Interrupt 3 - trap to debugger Flags modified: IF, TF, AC
Instruction_IRET	Intel opcode CF Interrupt return.
Instruction_JB_JNAE_JC	Intel opcode 72 Conditional short jump on carry.
Instruction_JB_JNAE_JC_long	Intel opcode OF 82 Conditional long jump on carry.
Instruction_JBE_JNA	Intel opcode 76 Conditional short jump on carry or zero.
Instruction_JCXZ_JECXZ	Intel opcode E3 Conditional short jump if CX is zero.
Instruction_JL_JNGE	Intel opcode 7C Conditional short jump if sign !
Instruction_JLE_JNG	Intel opcode 7E Conditional short jump if zero or sign !
Instruction_JMP_farAP	Intel opcode EA Unconditional absolute far jump indicated by immediate two words.
Instruction_JMP_nearJv	Intel opcode E9 Unconditional relative near jump indicated by immediate signed word.
Instruction_JMP_shortJb	Intel opcode EB Unconditional relative short jump indicated by immediate signed byte.
Instruction_JNB_JAE_JNC	Intel opcode 73 Conditional short jump not carry.
Instruction_JNB_JAE_JNC_long	Intel opcode OF 83 Conditional long jump on carry.
Instruction_JNBE_JA	Intel opcode 77 Conditional short jump not carry and not zero.
Instruction_JNL_JGE	Intel opcode 7D Conditional short jump if sign == overflow.
Instruction_JNLE_JG	Intel opcode 7F Conditional short jump if not zero and sign == overflow.
Instruction_JNO	Intel opcode 71 Conditional short jump not overflow.
Instruction_JNP_JPO	Intel opcode 7B Conditional short jump not parity / parity odd.
Instruction_JNS	Intel opcode 79 Conditional short jump not sign.
Instruction_JNZ_JNE	Intel opcode 75 Conditional short jump not zero.
Instruction_JNZ_JNE_long	Intel opcode 0F 85 Conditional long jump not zero.
Instruction_JO	Intel opcode 70 Conditional short jump on overflow.
Instruction_JP_JPE	Intel opcode 7A Conditional short jump on parity / parity even.
Instruction_JS	Intel opcode 78 Conditional short jump on sign.
Instruction_JZ_JE	Intel opcode 74 Conditional short jump on zero.
Instruction_JZ_JE_long	Intel opcode 0F 84 Conditional long jump on zero.
Instruction_LAHF	Intel opcode 9F Move low byte of the FLAGS register into AH register.
Instruction_LAR	Intel opcode F0 02 Load Access Rights byte.
Instruction_LDS_GvMp	Intel opcode C5 Load DS:r16 with far pointer from memory.
Instruction_LEA_GvM	Intel opcode 8D Load effective address computed from second operand (source) to register (destination).
Instruction_LEAVE	Intel opcode C9 LEAVE — High Level Procudure Exit.
Instruction_LES_GvMp	Intel opcode C4 Load ES:r16 with far pointer from memory.
Instruction_LOCK	Intel opcode 40 Increment general register AX.
Instruction_LODS_ALXb	Intel opcode AC Load byte from DS:SI into AL; update SI register according to DF.
Instruction_LODS_AXXv	Intel opcode AD Load word from DS:SI into AX; update DI register according to DF.
Instruction_LOOP_Jb	Intel opcode E2 Loop while CX is not zero, performing short jump indicated by immediate signed byte.
Instruction_LOOPE_LOOPZ_Jb	Intel opcode E1 Loop while CX is not zero and ZF == 1, performing short jump indicated by immediate signed byte.
Instruction_LOOPNE_LOOPNZ_Jb	Intel opcode E0 Loop while CX is not zero and ZF == 0, performing short jump indicated by immediate signed byte.
Instruction_MOV_ALOb	Intel opcode A0 Copy byte from DS:DISPL (DISPL given by word following opcode) to register AL.
Instruction_MOV_AXOv	Intel opcode A1 Copy word from DS:DISPL (DISPL given by word following opcode) to register AX.
Instruction_MOV_EbGb	Intel opcode 88 Byte-sized copy of memory/register (destination) from register (source).
Instruction_MOV_EvGv	Intel opcode 89 Word-sized copy of memory/register (destination) from register (source).
Instruction_MOV_EwSw	Intel opcode 8C Word-sized copy of memory/register (destination) from segment register (source).
Instruction_MOV_GbEb	Intel opcode 8A Byte-sized copy of register (destination) from memory/register (source).
Instruction_MOV_GvEv	Intel opcode 8B Word-sized copy of register (destination) from memory/register (source).
Instruction_MOV_Imm_AH	Intel opcode B4 Copy immediate byte to register AH.
Instruction_MOV_Imm_AL	Intel opcode B0 Copy immediate byte to register AL.
Instruction_MOV_Imm_AX	Intel opcode B8 Copy immediate word to register AX.
Instruction_MOV_Imm_BH	Intel opcode B7 Copy immediate byte to register BH.
Instruction_MOV_Imm_BL	Intel opcode B3 Copy immediate byte to register BL.
Instruction_MOV_Imm_BP	Intel opcode BD Copy immediate word to register BP.
Instruction_MOV_Imm_BX	Intel opcode BB Copy immediate word to register BX.
Instruction_MOV_Imm_CH	Intel opcode B5 Copy immediate byte to register CH.
Instruction_MOV_Imm_CL	Intel opcode B1 Copy immediate byte to register CL.
Instruction_MOV_Imm_CX	Intel opcode B9 Copy immediate word to register CX.
Instruction_MOV_Imm_DH	Intel opcode B6 Copy immediate byte to register DH.
Instruction_MOV_Imm_DI	Intel opcode BF Copy immediate word to register DI.
Instruction_MOV_Imm_DL	Intel opcode B2 Copy immediate byte to register DL.
Instruction_MOV_Imm_DX	Intel opcode BA Copy immediate word to register DX.
Instruction_MOV_Imm_SI	Intel opcode BE Copy immediate word to register SI.
Instruction_MOV_Imm_SP	Intel opcode BC Copy immediate word to register SP.
Instruction_MOV_ObAL	Intel opcode A2 Copy byte from register AL to DS:DISPL (DISPL given by word following opcode).
Instruction_MOV_OvAX	Intel opcode A3 Copy word from register AX to DS:DISPL (DISPL given by word following opcode).
Instruction_MOV_SwEw	Intel opcode 8E Word-sized copy of segment register (destination) from memory/register (source).
Instruction_MOVS_XbYb	Intel opcode A4 Move string byte at address DS:(E)SI to address ES:(E)DI.
Instruction_MOVS_XvYv	Intel opcode A5 Move string word at address DS:(E)SI to address ES:(E)DI.
Instruction_MOVZX_GvEw	Intel opcode F0 B7 Move with zero extend.
Instruction_NOP	Intel opcode 90 No operation, does not affect machine content except IP register.
Instruction_NULL
Instruction_Opd_Size	Intel opcode 66 Instruction prefix, indicating the next instruction should work with doublewords.
Instruction_OR_ALIb	Intel opcode 0C Logical OR of immediate byte and AL.
Instruction_OR_AXIv	Intel opcode 0D Logical OR of immediate word and AX.
Instruction_OR_EbGb	Intel opcode 08 Logical byte-sized OR of memory/register (destination) and register (source).
Instruction_OR_EvGv	Intel opcode 09 Logical word-sized OR of memory/register (destination) and register (source).
Instruction_OR_GbEb	Intel opcode 0A Logical byte-sized OR of register (destination) and memory/register (source).
Instruction_OR_GvEv	Intel opcode 0B Logical word-sized OR of register (destination) and memory/register (source).
Instruction_OUT_DXAL	Intel opcode EE Output byte in AL to I/O port address specified by DX.
Instruction_OUT_DXeAX	Intel opcode EF Output word/doubleword in eAX to I/O port address specified by DX.
Instruction_OUT_IbAL	Intel opcode E6 Output byte in AL to I/O port address indicated by immediate byte.
Instruction_OUTS_DXXb	Intel opcode 6E Output byte from DS:SI to I/O port (specified in DX); update SI register according to DF.
Instruction_OUTSW_DXXv	Intel opcode 6F Output word from DS:(E)SI to I/O port (specified in DX); update SI register according to DF.
Instruction_POP_AX	Intel opcode 58 Pop word from stack SP:SS into general register AX.
Instruction_POP_BP	Intel opcode 5D Pop word from stack SP:SS into general register BP.
Instruction_POP_BX	Intel opcode 5B Pop word from stack SP:SS into general register BX.
Instruction_POP_CX	Intel opcode 59 Pop word from stack SP:SS into general register CX.
Instruction_POP_DI	Intel opcode 5F Pop word from stack SP:SS into general register DI.
Instruction_POP_DS	Intel opcode 1F Pop word from stack SP:SS into general register DS.
Instruction_POP_DX	Intel opcode 5A Pop word from stack SP:SS into general register DX.
Instruction_POP_ES	Intel opcode 07 Pop word from stack SP:SS into general register ES.
Instruction_POP_Ev	Intel opcode 8F Pop word or double word from stack SP:SS into current segment at given offset (mem/reg).
Instruction_POP_SI	Intel opcode 5E Pop word from stack SP:SS into general register SI.
Instruction_POP_SP	Intel opcode 5C Pop word from stack SP:SS into general register SP.
Instruction_POP_SS	Intel opcode 1F Pop word from stack SP:SS into general register SS.
Instruction_POPA	Intel opcode 61 Pop top 8 words off stack into general purpose registers The order is DI, SI, BP, SP, BX, DX, CX, AX The SP value popped from the stack is discarded Flags modified: none
Instruction_POPF	Intel opcode 9D Pop word from stack into FLAGS register.
Instruction_PUSH_AX	Intel opcode 50 Push general register AX onto stack SS:SP.
Instruction_PUSH_BP	Intel opcode 55 Push general register BP onto stack SS:SP.
Instruction_PUSH_BX	Intel opcode 53 Push general register BX onto stack SS:SP.
Instruction_PUSH_CS	Intel opcode 0E Push general register CS onto stack SS:SP.
Instruction_PUSH_CX	Intel opcode 51 Push general register CX onto stack SS:SP.
Instruction_PUSH_DI	Intel opcode 57 Push general register DI onto stack SS:SP.
Instruction_PUSH_DS	Intel opcode 1E Push general register DS onto stack SS:SP.
Instruction_PUSH_DX	Intel opcode 52 Push general register DX onto stack SS:SP.
Instruction_PUSH_ES	Intel opcode 06 Push general register ES onto stack SS:SP.
Instruction_PUSH_Ib	Intel opcode 6A Push immediate byte onto stack SS:SP.
Instruction_PUSH_Iv	Intel opcode 68 Push immediate word onto stack SS:SP.
Instruction_PUSH_SI	Intel opcode 56 Push general register SI onto stack SS:SP.
Instruction_PUSH_SP	Intel opcode 54 Push general register SP onto stack SS:SP.
Instruction_PUSH_SS	Intel opcode 16 Push general register SS onto stack SS:SP.
Instruction_PUSHA	Intel opcode 60 Push all general purpose registers onto stack SS:SP.
Instruction_PUSHF	Intel opcode 9C Transfer FLAGS register onto stack SS:SP.
Instruction_REP_REPE	Intel opcode F3 Repeat execution of string instruction until CX == 0 or ZF is set.
Instruction_REPNE	Intel opcode F2 Repeat execution of string instruction until CX == 0 or ZF is set.
Instruction_RETF	Intel opcode CB Far (intersegment) return to calling procedure.
Instruction_RETF_Iw	Intel opcode CA Far (intersegment) return to calling procedure and pop bytes from stack Transfer control to return address located at top stack, and release a number of stack bytes Flags modified: none
Instruction_RETN	Intel opcode C3 Near (intrasegment) return to calling procedure.
Instruction_RETN_Iw	Intel opcode C2 Near (intrasegment) return to calling procedure.
Instruction_SAHF	Intel opcode 9E Load the FLAGS register with values from AH register.
Instruction_SBB_ALIb	Intel opcode 1C Subtract (immediate byte + CF) from AL.
Instruction_SBB_AXIv	Intel opcode 1D Subtract (immediate word + CF) from AX.
Instruction_SBB_EbGb	Intel opcode 18 Subtract byte (+ CF) in register (source) from memory/register (destination).
Instruction_SBB_EvGv	Intel opcode 19 Subtract word in register (source) + CF from memory/register (destination).
Instruction_SBB_GbEb	Intel opcode 1A Subtract byte in memory/register (source) + CF from register (destination).
Instruction_SBB_GvEv	Intel opcode 1B Subtract word in memory/register (source) + CF from register (destination).
Instruction_SCAS_ALYb	Intel opcode AE Compare AL with byte at ES:(E)DI and set status flags.
Instruction_SCAS_AXYv	Intel opcode AF Compare AX with word at ES:(E)DI and set status flags.
Instruction_SEG_CS	Intel opcode 2E Instruction SEG=CS.
Instruction_SEG_DS	Intel opcode 3E Instruction SEG=DS.
Instruction_SEG_ES	Intel opcode 26 Instruction SEG=ES.
Instruction_SEG_FS	Intel opcode 64 Segment selector FS.
Instruction_SEG_GS	Intel opcode 65 Segment selector GS.
Instruction_SEG_SS	Intel opcode 36 Instruction SEG=SS.
Instruction_ShiftGRP2_Eb1	Intel opcode D0 Immediate Group 2 opcode extension: ROL, ROR, RCL, RCR, SHL/SAL, SHR, SAR.
Instruction_ShiftGRP2_EbCL	Intel opcode D2 Immediate Group 2 opcode extension: ROL, ROR, RCL, RCR, SHL/SAL, SHR, SAR.
Instruction_ShiftGRP2_EbIb	Intel opcode C0 Immediate Group 2 opcode extension: ROL, ROR, RCL, RCR, SHL/SAL, SHR, SAR.
Instruction_ShiftGRP2_Ev1	Intel opcode D1 Immediate Group 2 opcode extension: ROL, ROR, RCL, RCR, SHL/SAL, SHR, SAR.
Instruction_ShiftGRP2_EvCL	Intel opcode D3 Immediate Group 2 opcode extension: ROL, ROR, RCL, RCR, SHL/SAL, SHR, SAR.
Instruction_ShiftGRP2_EvIb	Intel opcode C1 Immediate Group 2 opcode extension: ROL, ROR, RCL, RCR, SHL/SAL, SHR, SAR.
Instruction_STC	Intel opcode F9 Set carry flag.
Instruction_STD	Intel opcode FD Set direction flag.
Instruction_STI	Intel opcode FA Set interrupt flag.
Instruction_STOSB_YbAL	Intel opcode AA Copy byte from register AL to ES:DI; update DI register according to DF.
Instruction_STOSW_YvAX	Intel opcode AB Copy word from register AX to ES:DI; update DI register according to DF.
Instruction_SUB_ALIb	Intel opcode 2C Subtract immediate byte from AL.
Instruction_SUB_AXIv	Intel opcode 2D Subtract immediate word from AX.
Instruction_SUB_EbGb	Intel opcode 28 Subtract byte in register (source) from memory/register (destination).
Instruction_SUB_EvGv	Intel opcode 29 Subtract word in register (source) from memory/register (destination).
Instruction_SUB_GbEb	Intel opcode 2A Subtract byte in memory/register (source) from register (destination).
Instruction_SUB_GvEv	Intel opcode 2B Subtract word in memory/register (source) from register (destination).
Instruction_TEST_ALIb	Intel opcode A8 Logical comparison (AND) of immediate byte and AL.
Instruction_TEST_AXIv	Intel opcode A9 Logical comparison (AND) of immediate word and AX.
Instruction_TEST_EbGb	Intel opcode 84 Logical byte-sized comparison (AND) of memory/register ("destination") and register (source).
Instruction_TEST_EvGv	Intel opcode 85 Logical word-sized comparison (AND) of memory/register (destination) and register (source).
Instruction_UnaryGrp3_Eb	Intel opcode F6 Unary Group 3 opcode extension: TEST, NOT, NEG, MUL, IMUL, DIV, IDIV.
Instruction_UnaryGrp3_Ev	Intel opcode F7 Unary Group 3 opcode extension: TEST, NOT, NEG, MUL, IMUL, DIV, IDIV.
Instruction_XCHG_BPAX	Intel opcode 95 Exchange contents of registers BP and AX.
Instruction_XCHG_BXAX	Intel opcode 93 Exchange contents of registers BX and AX.
Instruction_XCHG_CXAX	Intel opcode 91 Exchange contents of registers CX and AX.
Instruction_XCHG_DIAX	Intel opcode 97 Exchange contents of registers DI and AX.
Instruction_XCHG_DXAX	Intel opcode 92 Exchange contents of registers DX and AX.
Instruction_XCHG_EbGb	Intel opcode 86 Byte-sized content exchange of memory/register (destination) and register (source).
Instruction_XCHG_EvGv	Intel opcode 87 Word-sized content exchange of memory/register (destination) and register (source).
Instruction_XCHG_SIAX	Intel opcode 96 Exchange contents of registers SI and AX.
Instruction_XCHG_SPAX	Intel opcode 94 Exchange contents of registers SP and AX.
Instruction_XLAT	Intel opcode D7 Set AL to memory byte DS:[BX + unsigned AL].
Instruction_XOR_ALIb	Intel opcode 34 Logical XOR of immediate byte and AL.
Instruction_XOR_AXIv	Intel opcode 35 Logical XOR of immediate word and AX.
Instruction_XOR_EbGb	Intel opcode 30 Logical byte-sized XOR of memory/register (destination) and register (source).
Instruction_XOR_EvGv	Intel opcode 31 Logical word-sized XOR of memory/register (destination) and register (source).
Instruction_XOR_GbEb	Intel opcode 32 Logical byte-sized XOR of register (destination) and memory/register (source).
Instruction_XOR_GvEv	Intel opcode 33 Logical word-sized XOR of register (destination) and memory/register (source).
Util