nl.kbna.dioscuri.module.cpu
Class Instruction_AND_GvEv

java.lang.Object
  nl.kbna.dioscuri.module.cpu.Instruction_AND_GvEv

All Implemented Interfaces:

Instruction

public class Instruction_AND_GvEv
extends java.lang.Object
implements Instruction

Intel opcode 23
Logical word-sized AND of register (destination) and memory/register (source).
The addressbyte determines the source (sss bits) and destination (rrr bits).
Flags modified: OF, SF, ZF, AF, PF, CF

Field Summary

(package private) byte	addressByte
private CPU	cpu
(package private) byte[]	destinationRegister
(package private) byte[]	memoryReferenceDisplacement
(package private) byte[]	memoryReferenceLocation
(package private) boolean	operandWordSize
(package private) byte[]	sourceValue

Constructor Summary

Instruction_AND_GvEv()
Class constructor

Instruction_AND_GvEv(CPU processor)
Class constructor specifying processor reference

Method Summary

void	execute() Logical AND of memory/register (destination) and register (source).

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

cpu

private CPU cpu

operandWordSize

boolean operandWordSize

addressByte

byte addressByte

memoryReferenceLocation

byte[] memoryReferenceLocation

memoryReferenceDisplacement

byte[] memoryReferenceDisplacement

sourceValue

byte[] sourceValue

destinationRegister

byte[] destinationRegister

Constructor Detail

Instruction_AND_GvEv

public Instruction_AND_GvEv()

Class constructor

Instruction_AND_GvEv

public Instruction_AND_GvEv(CPU processor)

Class constructor specifying processor reference

Parameters:

processor - Reference to CPU class

Method Detail

execute

public void execute()

Logical AND of memory/register (destination) and register (source).
OF and CF are cleared. AF is undefined.

Specified by:

execute in interface Instruction